document number: 37020 revision 05-dec-00 www.vishay.com 2 APD-256G064-1 vishay dale plasma panel display module 256 x 64 graphics display with drive electronics, ttl level data interfacer and integrated dc converter *recommended operating voltages. all maximums are absolute maximum. features ? ttl level video interface. ? on board dc converter. ? slim profile. ? large, bright characters and graphics. ? highly visible for long distance viewing. electrical specifications voltages required: vdc: + 12 to + 24 vdc. v cc : + 5 vdc. power required: typical = 12 watts, maximum = 45 watts. optical specifications viewing area: 12.75" [323.85] w x 4.24" [107.70] h. pixel pitch: 0.050" [1.27] h, 0.0666" [1.69] w. pixel size: 0.025" x 0.040" [0.635 x 1.016]. color: neon orange. text with typical 5x7 character matrix using 1 column between characters and 1 row between lines. maximum number of characters per line: 42. maximum number of lines: 16. maximum character size: .225 w x .439 h. luminance: 50 foot lamberts minimum. environmental specifications operating temperature: 0 c to + 70 c. storage temperature: - 40 c to + 85 c. relative operating humidity: to 95% non-condensing. mechanical shock: 30g. vibration: 3g. operating altitude: 10,000 feet. general description the APD-256G064-1 dc plasma display offers viewing qualities designers seek such as high contrast, viewing angle of 150 minimum, and long distance readability. it is bright (50 foot lamberts minimum) with characters and graphics figures presented in a pleasing neon orange color against a black background. plasma is much more read- able and eye-pleasing than liquid crystal or vacuum fluores- cent displays and is filterable to red, amber, or neutral density. these plasma display panels are driven in a standard row - column refresh method much like a crt display. the designer need only supply ttl level signals for serial data, dot clock, column latch, row data, row clock and display enable. the serial data is entered with the dot clock up to frequencies as high as 8mhz. after a row of 256 pixels is clocked in, the column latch signal is toggled and the data is latched. at the time the data is latched, the display is briefly disabled using the display enable signal, then the row pointer is advanced with the row clock signal. once each frame the row data must be asserted to synchronize the column serial data with the beginning row. the recommended scanning frequency is approximately 70 hz but may be as high as 200 hz. the high clock rate on the data clock allows for rapid refresh and maximum access time to the refresh ram. the APD-256G064-1 has been designed to offer high brightness and superior viewing aesthetics in a package that is very affordable. this display is ideal for low to medium level information content messages and would be ideal for applications such as arcade games, process control, pos terminals, medical equipment, message centers and atm machines. 3.001 [76.22] 5.986 [152.04] 5.686 [144.42] column 1, row 1 .150 [3.81] dia. 256 x 64 pixels 14.50 [368.3] 7.25 [184.15] 4.236 [107.60] 5.136 [130.45] .487 [12.37] .883 [22.43] 7.25 [184.15] 14.80 [375.92] 14.00 [355.60] 12.775 [324.49] dimensions in inches [millimeters] .150 [3.81] ? ? ? ? ? ? ? ? ? ? ? ? ? ? c l c l c l ? ? ? ? ? 6.750 [171.45] 8.775 [222.89] 7.40 [187.96] 10.50 [266.70] pin 1 of j3 pin 1 of p2 .062 [1.57] pcb thickness .447 .020 [11.35 .508] .150 [3.81] standard electrical specifications* description logic supply dc converter input dc converter power @ + 12v logic 1 input logic 0 input symbol v cc vdc amps v ih v il min. + 4.5 + 10 screen clear 0.100 2.0 typ. + 5.0 + 24.0 50% lit 1.7 max. + 5.5 + 28.0 100% lit 3.5 0.8 units vdc vdc vdc vdc
www.vishay.com 3 APD-256G064-1 vishay dale document number: 37020 revision 05-dec-00 description of input signals dot clock - this signal enters the serial data on each low to high transition. a total of 256 dot clock transitions must be present for each line of column/anode data. serial data - this signal presents the pixel data in positive logic format. a logic one represents a lit pixel and a logic zero represents an extinguished pixel. data is entered from right to left. the first pixel data entered will represent the leftmost pixel in the row. column latch - this signal latches the pixel data into the driver outputs. when the column latch signal goes to logic one the data entered previously will fall through to the driver outputs. when the signal returns to a logic zero, the data is latched and the shift register is now ready to accept the next row of data. must be held low while entering new serial data. display enable - this signal enables the output drivers. using a duty cycle control, this signal may also be used for intensity control. the display enable must be at logic zero before the column latch signal transitions. to avoid display blurring, the row clock signal should also transition while display enable is a logic zero. it is recommended that this signal remain low for 10 s min. row data - this signal is the first line marker for the scan. this input should be held high to correspond to the first row of pixel data. row clock - this signal clocks row data on the falling edge. the row clock signal is repetitive and must be present for proper scanning of the display module. the APD-256G064-1 has a unique input protection circuit that assures the column drivers stay blanked on power up. the protection circuit unblanks the column drivers when the row clock signal begins (i.e. the display begins scan- ning). ordering information display module with drivers, ttl interface and on board converter.............................................................. . ................ APD-256G064-1 data connector kit............................................................................................................. ......................................... ................ 280105-05 power connector kit............................................................................................................ ....................................... ................ 280108-13 video controller (+5v) parallel and serial interface........................................................................... ........................... ................. pds-500 video controller (+12v) parallel and serial interface.......................................................................... ....................... ................ pds-500-1 pin description p3, power connector pin 1 2 3 4 5 description v bb dc converter supply logic supply used to key connector v bb and v cc signal gnd vdc v cc key gnd amp #640445-5 or equivalent. (mates with amp 640428-5, molex 09-05-3051 or equivalent.) p2, data connector amp #103309-2 or equivalent. (mates with amp 746195-2, molex 39-27-1146 or equivalent.) description display enable row data row clock column latch dot clock serial data no connect pin 1 3 5 7 9 11 13 pin 2 4 6 8 10 12 14 description ground ground ground ground ground ground ground display enable logic and data timing serial data dot clock t 7 1st bit of row will appear in leftmost column 0 1 2 254 255 t 6 t 5 positive edge x 256 row data row clock display enable 0 t 2 t 1 t 4 1 63 62 2 1 0 63 62 2 1 0 t 3 01 row clock column latch parameter t 1 t 2 t 3 t 4 t 5 t 6 t 7 minimum 100 5 1 25 75 75 typical 70 maximum 200 units ns us us hz ns ns ns
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